Signal Integrity and High-Speed Digital: Jitter, Eye Diagrams, BER, Serial Decode

This page collects AXMEAS Signal's field notes and explainers on signal integrity and high-speed digital measurement: jitter decomposition, eye diagrams and masks, bit error ratio, PAM4, de-embedding, compliance testing for USB, Ethernet, DDR and MIPI, and protocol decoding of I2C, SPI and automotive buses. Many articles start from a real oscilloscope or BERT screen at Embedded World, electronica or other shows and check whether its numbers are consistent.

Recurring themes: why total jitter at 1e-12 is a model extrapolated many decades beyond the captured data; how to recognise the line code (NRZ, MLT-3, PAM4) from the eye alone; why fixtures and probes must be de-embedded before a measurement describes the silicon; and why protocol decode and physical-layer analysis belong on the same screen.

Frequently asked questions

How do I check a jitter table for consistency?

Under the dual-Dirac model, total jitter at a BER of 1e-12 is approximately Dj(dd) + 14.07 x Rj. If the displayed Tj does not match this sum, the rows probably come from different models, BER targets or units.

Why does a 100BASE-TX eye have three levels?

100BASE-TX uses MLT-3 line coding, which steps through +1, 0, -1, 0, so the eye shows three rails and two stacked openings. 1000BASE-T uses five-level PAM-5; PAM4 interfaces show three eyes.

How long must a BER test run?

To claim a BER below a target with about 95 % confidence and zero errors, roughly 3 / BER bits are needed: 3e12 bits for 1e-12. Links that run with forward error correction instead measure a non-zero pre-FEC BER, which converges much faster.

Why is the NACK at the end of an I2C read not an error?

The master acknowledges every byte it wants to continue reading and sends a NACK after the last one, before the stop condition. A NACK on the address byte or during a write indicates a real problem.

See also: Power electronics · RF and microwave · About AXMEAS Signal