Every AI server, every edge computing platform, every modern ECU has one thing in common: it runs on DDR memory and high-speed serial interfaces. And every one of them depends on something most software engineers never think about — the quality of the signal carrying the data.
At Embedded World 2026, Rohde & Schwarz ran a live high-speed interface testing demo that made this dependency impossible to ignore. Here is what was happening on that bench, and why it matters for anyone building systems that push data at the speed modern applications demand.
R&S High Speed Interface Testing for DDR and USB demo — Embedded World 2026, Nuremberg. Left: R&S RTP164B with DDR eye diagram. Right: R&S MXO38. Center display shows Automated Compliance Testing capability. Photo: Thomas — Follow on X: @SignalByThomas
At High Speed, There Is No Digital
This is the fundamental insight that this demo communicates better than any whitepaper could.
DDR5 operates at up to 6400 MT/s. At that speed, one bit occupies approximately 156 picoseconds in time. USB4 runs at 40 Gbps. PCIe Gen5 at 32 GT/s.
At these data rates, the signal is no longer the clean square wave a logic textbook describes. It is an analog waveform subject to:
→ Jitter — timing uncertainty that shifts bit edges
→ Noise — amplitude variations that blur the signal levels
→ Reflections — impedance discontinuities that send energy back down the line
→ Crosstalk — interference from adjacent signal lines
The digital abstraction — ones and zeros — only holds if the underlying analog behavior stays within tightly defined limits. When it does not, the system fails. Not sometimes. Always.
The Test Setup: A Real System Under Real Stress
What made this demo particularly instructive was the choice of DUT: not an evaluation board, but a complete working PC motherboard running inside a transparent acrylic enclosure.
The DUT — Intel Core i7-12700K system
An ASUS motherboard with an Intel 12th Gen Core i7-12700K processor and Kingston DDR5-4800 memory was running PassMark MemTest86 Pro — a memory stress tool that continuously generates random read/write patterns across all memory addresses. Pass 149 of 999, cumulative error count: 0. This is the DUT generating authentic, sustained DDR traffic — not a synthetic pattern from a signal generator.
The reason for this choice is significant: only a real system running real memory access patterns produces the full range of signal integrity effects that engineers need to characterize. Crosstalk between data lines, power supply noise coupling into the memory bus, thermal effects on timing margins — none of these appear in a synthesized test signal.
The oscilloscope — R&S RTP164B
The primary instrument was the R&S RTP164B: 16 GHz bandwidth, 40 GSa/s sample rate. Probing a DDR5 bus at 4800 MHz requires bandwidth well above the fundamental frequency — the third and fifth harmonics of the clock fall at 14.4 GHz and 24 GHz respectively. The oscilloscope screen showed a multi-channel view: the DQS strobe signal at the top, the DQ Eye - Write diagram in the center — an X-shaped overlay of thousands of write transitions — and the decoded DQ signal at the bottom.
R&S RTP164B (16 GHz / 40 GSa/s) displaying live DDR5 DQ Eye Write diagram. Left screen: PassMark MemTest86 Pro running on Intel i7-12700K with Kingston DDR5-4800, Pass 149/999, zero errors. Right display: Signal Integrity Debugging tools. Photo: Thomas — Follow on X:@SignalByThomas
What the Eye Diagram Tells You
The DDR eye diagram is the single most information-dense view available for memory signal integrity analysis. It is formed by overlaying thousands of consecutive bit transitions, time-aligned to the strobe signal. The resulting X-shape reveals everything:
→ Eye height — the vertical opening between ones and zeros. Smaller means less noise margin.
→ Eye width — the horizontal opening at the crossing point. Smaller means less timing margin.
→ Transition density — the color map shows where most transitions fall. Hot spots outside the eye indicate recurring violations.
→ Jitter spread — the width of the crossing region. Wide spread means high jitter.
The JEDEC DDR standard defines a mask — a forbidden region the signal must never enter. The compliance test checks this automatically across millions of transitions. The result is binary: PASS or FAIL.
The DUT: a complete Intel Core i7-12700K motherboard with DDR5-4800 memory inside a transparent acrylic enclosure, running PassMark MemTest86 Pro under full memory stress. This real-system approach generates authentic DDR traffic that evaluation boards cannot replicate. Photo: Thomas — Follow on X:@SignalByThomas
Signal Integrity Debugging: Finding the Root Cause
The right display screen showed the R&S Signal Integrity Debugging capability, listing three key tools:
→ Zone Trigger — draw a zone on the waveform display and trigger only when a signal enters or exits that region. This captures the specific conditions that cause timing violations, rather than waiting for random failures.
→ Deembedding of Interposer — mathematically removes the effect of the probe interposer from the measurement, so the result reflects the true signal at the DDR component pins.
→ Advanced Eye Analysis and Jitter Decomposition — separates total jitter into its components: random jitter (RJ), deterministic jitter (DJ), periodic jitter (PJ), and data-dependent jitter (DDJ). Each has a different root cause and requires a different fix.
This last capability is where debugging becomes genuinely powerful. A system showing 20 ps of total jitter might have 5 ps of random jitter — acceptable — and 15 ps of deterministic jitter from a specific aggressor net. Finding and fixing that aggressor is only possible once you can separate the components.
Automated Compliance Testing
The center display showed the R&S automated compliance testing capability for DDR4/LPDDR4 and DDR5/LPDDR5 — the full JEDEC test suite executed automatically, producing a structured PASS/FAIL report. The suite supports:
→ System-level testing for LPDDR5, LPDDR4 and LPDDR5
→ Automated Compliance, Read/Write Decode and Eye Diagram in one operation
→ Comprehensive Signal Integrity Debugging Tools
A manual DDR compliance test run takes a skilled engineer a full day. The automated suite runs overnight and produces a traceable, standards-referenced report. For teams shipping products that must pass JEDEC certification, this is not a convenience — it is a requirement.
Full bench overview: transparent PC DUT (left), R&S RTP164B oscilloscope (center), R&S MXO38 (right). Center display: DDR Memory Interface Verification and Debugging — supporting LPDDR4/5 and DDR5 system-level testing. Photo: Thomas — Follow on X: @SignalByThomas
Why This Matters Beyond Memory
The techniques shown in this demo apply directly to the full range of high-speed interfaces that define modern system performance:
→ PCIe Gen5 at 32 GT/s — the backbone of AI accelerator cards in every GPU server
→ USB4 at 40 Gbps — the external interface standard for next-generation embedded systems
→ LPDDR5 in mobile and automotive — where power constraints make signal margins even tighter
→ SerDes links in FPGAs and ASICs — custom high-speed connections that require creative fixturing
In every case, the underlying physics is the same: fast edges, tight timing, analog behavior pretending to be digital.
The Observation That Should Shape Your Testing Strategy
R&S chose to demonstrate DDR memory testing using a real, populated, running PC motherboard — not a simplified evaluation board. This was a deliberate choice that communicates something important: the signal integrity problems that matter are the ones that appear in complete systems under real operating conditions, not the ones visible in clean lab setups.
A DDR5 design that passes every margin check on a bare evaluation board may still exhibit timing violations in the final product — when the board is populated, the power rails are loaded, the thermal environment is elevated, and adjacent circuits are switching simultaneously.
The teams that catch this gap — between what a clean lab measurement shows and what a production system actually experiences — are the ones that ship reliable products on the first revision.
The AI server of today, the edge device of next year, and the automotive ECU of the next decade all depend on the same thing: signals that arrive on time, at the right level, every single time. Testing that is not a luxury — it is the engineering discipline that makes everything else possible.
Observed live at Embedded World 2026, Nuremberg. Equipment: R&S RTP164B (16 GHz / 40 GSa/s). DUT: Intel Core i7-12700K with Kingston DDR5-4800, running PassMark MemTest86 Pro. All photos by Thomas — Follow on X: @SignalByThomas