At Embedded World 2026, I stopped at a Rohde & Schwarz demo that looked almost too simple.
A green PCB. No chips. No connectors to a larger system. Just structures — traces, vias, differential pairs — probed by two SMA cables leading to a VNA screen filled with curves.
The booth title said: SIGNAL INTEGRITY: ELECTRONIC DESIGN TEST
Simple words. But the engineering behind it goes very deep.
The Fundamental Problem at GHz Speeds
Traditional design thinking treats PCB traces as wires — passive, transparent, invisible to the signal. This assumption works fine at low frequencies.
At high speeds, it fails completely.
When signal wavelengths approach the physical dimensions of PCB structures, traces stop behaving like conductors and start behaving like transmission lines. The implications are significant:
→ A differential pair with wrong geometry doesn't just "carry" a signal
→ It reflects part of it back to the source
→ It attenuates what gets through
→ It distorts phase relationships
→ It couples energy into adjacent traces
This is not a simulation artifact. It is physical reality — and it happens in every high-speed system being designed today.
Photo: Thomas · @SignalByThomas
The Instrument: R&S ZNB Vector Network Analyzer (9 kHz – 43.5 GHz)
The device at the center of this demo was a Rohde & Schwarz ZNB Vector Network Analyzer, operating from 9 kHz up to 43.5 GHz.
A VNA is the primary instrument for characterizing how electrical networks respond to signals across frequency. The measurement method is straightforward in concept:
→ Port 1 injects a known signal into the PCB structure
→ Port 2 receives whatever exits the other end
→ The VNA measures the ratio — in both magnitude and phase — across the entire frequency sweep
The result is a set of S-parameters — scattering parameters — that fully characterize the structure's electrical behavior.
S-Parameters: What They Actually Tell You
S-parameters are the language of signal integrity. Here's what each one means in practice:
S11 — Return Loss (reflection at Port 1)
→ How much signal bounces back from the structure
→ High S11 means impedance mismatch — energy is being reflected, not transmitted
→ Target: below −10 dB across the operational bandwidth
S21 — Insertion Loss (transmission from Port 1 to Port 2)
→ How much signal actually gets through
→ Every dB of insertion loss is signal that didn't reach its destination
→ For a PCIe Gen5 channel, this budget is tightly constrained
S12 / S22
→ Reverse transmission and output reflection
→ Critical for understanding bidirectional channel behavior
On the ZNB screen, you could see both curves clearly: the |S21| magnitude trace showing frequency-dependent attenuation, and a TDR-derived view revealing impedance discontinuities in the time domain. Two windows, same physical structure — frequency domain and time domain simultaneously.
The Test Fixture: A PCB Designed to Fail (Intentionally)
The green board on the table was not a prototype product. It was a Signal Integrity test fixture — a PCB designed specifically to present known structures for measurement.
Each section corresponded to a different design element:
→ Microstrip lines — surface traces over a ground plane
→ Striplines — buried traces between two ground planes
→ Differential pairs — matched traces for SerDes signals
→ Via transitions — the transition from one layer to another
→ Connector launches — where the PCB meets the cable or mating connector
Each of these is a known SI problem area. Vias create impedance discontinuities. Connector launches create reflections. Differential pairs must maintain tight geometry to preserve common-mode rejection. The test fixture makes every one of these measurable, quantifiable, and comparable against specification.
Why Simulation Alone Is Not Enough
A common question: can't you just simulate this in a field solver?
The answer is: simulation is necessary, but not sufficient.
Simulation models an idealized geometry. Real PCBs introduce variables that are difficult or impossible to model precisely:
→ Dielectric constant (Dk) variation — PCB laminates vary between batches and even within a panel
→ Copper roughness — surface roughness increases loss at high frequencies, often more than models predict
→ Via stub resonances — unterminated via barrels create frequency-specific notches in S21
→ Manufacturing tolerances — trace width and spacing variations shift impedance from target
Measurement closes the loop. It tells you not what you designed, but what you built — and whether those two things are close enough to work.
The Frequency Landscape That Makes This Necessary
The interfaces driving modern system design are all operating at frequencies where SI is the dominant design constraint:
→ PCIe Gen5 / Gen6 — 16 to 32 GHz signaling rates
→ DDR5 memory — data rates exceeding 6 Gbps, with clock harmonics into the GHz range
→ USB4 / Thunderbolt — 20 GHz channel requirements
→ 100G / 400G Ethernet — SerDes lanes operating at 26+ GHz per lane
→ Automotive high-speed Ethernet (1000BASE-T1, 10GBASE-T1) — in-vehicle ECU interconnects under strict SI masks
For every one of these interfaces, the PCB channel is a defined specification. The VNA measurement determines whether that specification is met — before the system goes into production.
Where This Matters in Real System Design
The demo at Embedded World 2026 was positioned as a signal integrity solution for electronic design validation — not production test, not field service. The target is the engineering team during PCB development.
In practice, this type of measurement is used in three phases:
1. Stackup validation
→ Before routing, verify that the proposed PCB stackup achieves target impedance (typically 50Ω single-ended, 100Ω differential)
→ Measured on coupon structures, not functional circuits
2. Channel characterization
→ After first hardware build, measure end-to-end channel S-parameters
→ Convert to time domain (TDR/TDT) to identify specific discontinuities
→ Correlate with simulation — if they match, the model is trusted; if they don't, the model needs revision
3. Compliance verification
→ Final check against interface specification (e.g., PCIe Base Specification channel masks)
→ Often required before silicon bring-up to rule out PCB as a failure source
The Calibration Problem: Why Accuracy Is Hard
A VNA is only as accurate as its calibration. At 43 GHz, cable losses, connector variations, and instrument port reflections all contribute to measurement error — and these errors compound at high frequencies.
Calibration standards such as SOLT (Short-Open-Load-Thru) and TRL (Thru-Reflect-Line) are used to mathematically remove instrument and fixture effects from the measurement. TRL is particularly powerful for PCB fixture calibration because it uses transmission lines on the same substrate — accounting for real dielectric properties rather than ideal standards.
The calibration kit in the demo was a separate line item — and a significant one. Precision calibration at 43 GHz requires mechanical tolerances that are genuinely difficult to achieve.
The Industry Direction: From Device Sales to Validation Workflow
What Rohde & Schwarz was selling at this booth was not a VNA in isolation. It was a complete SI validation workflow:
→ VNA hardware (R&S ZNB series)
→ High-precision test cables and connectors
→ Calibration kit matched to the frequency range
→ SI-specific software for de-embedding, time-domain transform, and compliance checking
This pattern — instrument as part of a broader application solution — is visible across the T&M industry right now. The device alone has limited value. The workflow it enables is the product.
For embedded systems companies entering high-speed interface design for the first time, this is a significant investment decision: not just "should we buy a VNA" but "do we have the SI measurement methodology to use it effectively."
What I Took Away from This Demo
The insight that stays with me is not about the VNA itself. It's about where design authority actually sits in modern electronics.
As data rates increase, the signal path through the PCB becomes the dominant variable. Not the IC. Not the firmware. Not the power supply.
The trace. The via. The connector launch.
These are now engineered components, not routing artifacts. They have specifications. They must be measured. They can fail independently of every other element in the system.
The demo made that visible in a way that a datasheet never could: a physical board with no chips, generating S-parameter curves that tell you exactly how much signal survives the journey from one end to the other.
That's signal integrity. And at current data rates, it's not optional.
Instrument: Rohde & Schwarz ZNB Vector Network Analyzer · 9 kHz – 43.5 GHz
Measurement: S-parameters (S11, S21, S12, S22) · TDR/TDT analysis
Application: Signal Integrity Design Validation · High-Speed PCB Characterization
Seen at: Embedded World 2026, Nuremberg
All photos: Thomas · @SignalByThomas