There is a persistent assumption in hardware engineering that signal problems come from signal sources. Bad routing. Wrong termination. Inadequate bandwidth. Fix the signal path, fix the problem.
This assumption is increasingly wrong — and the consequences of holding onto it are becoming more expensive as systems get faster and more complex.
At Embedded World 2026, Tektronix dedicated a significant portion of their booth to a single proposition: Signal integrity and power integrity are not two disciplines. They are one system. And the demo backing this up drew some of the largest crowds I saw at the show.
The Physics Nobody Wants to Talk About
Here is the chain that most engineers understand conceptually but rarely measure in practice:
→ A switching power supply or a high-current load transient creates voltage ripple on a power rail
→ That ripple couples into the substrate of every IC powered from that rail
→ Inside those ICs, the PLL — the circuit that generates and locks onto clock signals — is highly sensitive to its supply voltage
→ Voltage ripple on the PLL supply becomes phase noise and jitter on the clock output
→ That jitter propagates into every data signal clocked by that reference
→ At the receiver, jitter reduces timing margin and increases bit error rate
The signal failed. But the root cause was in the power domain.
This is not a hypothetical. It is one of the most common root causes of intermittent failures in high-speed digital systems — and one of the hardest to diagnose if you are only looking at the signal domain.
Why This Matters Now More Than Ever
The reason this coupling has become critical — and why Tektronix has made it a strategic messaging pillar — is the convergence of three trends:
Supply voltages are dropping while sensitivity is rising. Modern AI accelerators and high-performance SoCs operate at core voltages of 0.7V to 0.9V. At these voltages, a 1 mV ripple represents 0.1–0.15% of the supply. That same 1 mV on a 3.3V rail 20 years ago was negligible. Today it is not.
Current demands are becoming more dynamic. A GPU running an AI inference workload does not draw constant current. It draws current in bursts — sharp, high-amplitude transients that follow the rhythm of matrix multiplication operations. These transients are essentially current-domain signals, and they couple into voltage rails through the impedance of the power delivery network (PDN). The faster the transient, the higher the impedance at those frequencies, and the larger the voltage deviation.
Clock frequencies and data rates are pushing into the tens of gigabits per second. At 56G PAM4 or 112G PAM4 SerDes speeds, the unit interval — the time allocated to one symbol — is 17.8 picoseconds or 8.9 picoseconds respectively. Jitter budgets are measured in femtoseconds. A PLL that is even slightly disturbed by supply noise can consume the entire jitter margin of a high-speed link.
What "Measure Ultra-Low Ripple Down to µV" Actually Means
The Tektronix booth wall stated it directly: Measure ultra-low ripple down to µV. Analyze high-switching noise across multiple domains.
This is not marketing language. It is a technical specification requirement driven by the physics described above.
Measuring µV-level ripple on a power rail in a real system is genuinely difficult. The challenges are:
→ Common-mode noise: The power rail and ground reference are both noisy. A single-ended measurement picks up both signal and noise indiscriminately. Differential measurement with high common-mode rejection is required.
→ Probe loading: Any probe connected to a high-impedance node changes the impedance of that node. On a power rail, probe inductance can resonate with decoupling capacitors and create measurement artifacts that look like real signals.
→ Oscilloscope noise floor: A standard oscilloscope channel at 50 mV/div has a noise floor that may already be larger than the ripple being measured. This is where ENOB — Effective Number of Bits — determines whether the measurement is meaningful or meaningless.
The "New High BW Shunts" featured prominently at the booth address the second problem directly. A high-bandwidth shunt resistor — placed in series with the supply rail — converts the current flowing through the rail into a voltage that can be measured differentially. Compared to a clip-on current probe, a precision shunt offers higher bandwidth, lower insertion inductance, and significantly better noise performance. The trade-off is that it requires modification of the circuit under test. For characterization work, that trade-off is almost always worth making.
The Embedded Debugging Layer
The second demo on the Tektronix bench brought the other end of the measurement spectrum into focus: a Tektronix 4 Series MSO connected to embedded development boards, performing live protocol decoding.
The oscilloscope screen showed something that instantly communicates its value to any embedded engineer: raw waveforms at the top, decoded protocol data below — Data:60h, Data:54h — with the bus type selector showing the breadth of supported protocols: SPI, Auto Ethernet, EtherCAT, SPMI, MIL-STD-1553, ARINC429, SpaceWire, MDIO, and more.
The significance of this is subtle but important. Protocol decoding is not just a convenience feature. It is the bridge between the physical layer and the application layer. When a register write fails intermittently, the waveform alone tells you that something went wrong. The decoded packet tells you what the system was trying to do when it went wrong. These two pieces of information together — the analog behavior and the digital intent — are what makes debugging tractable instead of speculative.
In the context of the SI/PI theme: power rail disturbances that cause timing violations will appear as protocol decode errors. The engineer who can see both the power rail noise and the resulting protocol anomaly in the same time base — correlated, synchronized — can close the diagnostic loop in minutes instead of days.
Tektronix 4 Series MSO performing live protocol decoding on embedded development boards. Background display shows decoded bus data (Data:60h). The bench setup illustrates the transition from physical-layer waveforms to application-layer protocol visibility. Photo: Thomas · @SignalByThomas
The System-Level Shift: From Measurement to Understanding
What Tektronix demonstrated at Embedded World 2026 is a measurement philosophy that reflects where the industry is heading: away from isolated single-domain measurements and toward system-level observability.
In practice, this means:
→ Synchronized multi-domain capture: Power rail, clock signal, and data signal captured simultaneously in the same acquisition window, with common time reference. When the power rail dips, the jitter increase appears on the clock at the same timestamp. Causality becomes visible.
→ Cross-domain correlation: Statistical tools that correlate power rail events with signal integrity metrics. Instead of asking "is there jitter?", the question becomes "does jitter increase when the CPU core transitions from idle to active?"
→ Signal integrity modeling: The "New Signal Integrity Modeling" capability highlighted on the booth wall allows engineers to build channel models from measured S-parameters and apply them in simulation, validating design choices before physical hardware exists.
Tektronix 4 Series MSO screen showing the full protocol decode configuration panel: SPI, Auto Ethernet, EtherCAT, SPMI, MIL-STD-1553, ARINC429, SpaceWire, MDIO — and decoded result Data:60h. The breadth of supported protocols reflects the scope of embedded debugging requirements. Photo: Thomas · @SignalByThomas
Where This Applies Beyond the Lab Bench
The techniques and capabilities shown in this demo have direct application in the systems that define the next decade of electronics:
AI accelerator boards and GPU clusters
A modern GPU draws hundreds of amperes from a sub-1V supply. The current transients during AI workload execution are some of the most aggressive switching events in consumer and datacenter electronics. Power delivery network design — the placement of decoupling capacitors, the impedance profile of the board, the bandwidth of the voltage regulator — directly determines the jitter performance of the GPU's high-speed interfaces. Measuring this requires exactly the µV-level, high-bandwidth, synchronized SI/PI capability that this demo showed.
High-speed memory subsystems
DDR5 and LPDDR5 memory interfaces are among the most PDN-sensitive circuits in modern systems. The VDDQ and VPP rails power the memory I/O directly. Noise on these rails — even at the 100 µV level — affects the read and write timing margins that determine whether the memory interface is reliable. AI inference servers running 24/7 under thermal load are particularly vulnerable to PDN degradation over time.
Automotive and functional safety systems
Automotive ECUs must meet functional safety standards (ISO 26262) that require deterministic behavior under all operating conditions. Power rail integrity is a mandatory verification item. A signal that meets timing specifications in a clean lab environment may fail in a vehicle under full electrical load. Catching that failure mode requires exactly the kind of system-level correlation between power and signal domains that this demo demonstrated.
The Measurement Discipline That Is Still Being Built
Here is an honest assessment of where the industry stands: the tools exist. The physics is well understood. But the engineering discipline of treating SI and PI as a unified measurement problem is still being built in most organizations.
Most hardware teams have separate signal integrity engineers and power integrity engineers. They use different tools, speak different languages, and hand off to each other rather than measuring together. The result is that cross-domain failure modes — which are some of the most common and most expensive — fall into the gap between the two disciplines.
The demo at Embedded World was not just showing what Tektronix oscilloscopes can do. It was illustrating what a mature measurement practice looks like — and what becomes possible when the two domains are treated as one.
Power noise does not stay in the power domain. It becomes timing uncertainty. Timing uncertainty becomes bit errors. Bit errors become system failures. The chain is short. The measurement discipline to see it is not yet universal — but it is becoming necessary.
Observed live at Embedded World 2026, Nuremberg. Tektronix booth featuring "Bridging Signal and Power Integrity for High-Speed Design." Equipment: Tektronix 7 Series MSO, Tektronix 4 Series MSO, New High BW Shunts. All photos: Thomas · @SignalByThomas