When you stand in front of a well-designed demo, everything looks connected.
An oscilloscope. A source measurement unit. High-bandwidth isolated probes. A transparent DUT fixture showing the actual switching circuit.
Tektronix and Keithley brought exactly that setup to PCIM Europe — two separate stations, each addressing a completely different problem.
→ Static DC Characterization for Power Devices → Dynamic Switching Power Characterization (DPT)
They look like two halves of the same workflow. They are not.
Station 1 → Keithley: Quantifying Trapped Charges in SiC MOS Devices
The display on the wall said it clearly:
"Quantify Trapped Charges on SiC MOS Devices — Using the Patent Pending Forced Current Quasistatic CV Method"
This is not a standard CV measurement. This is a method specifically developed to expose what conventional sweeps miss.
The test fixture on the bench was a Keithley shielded measurement enclosure, wired to a 4200A-SCS semiconductor characterization platform. Next to it: a 2657A High Power System SourceMeter — capable of up to 3,000 V and 180 W continuous.
The display readout: 00.0017 nA / -000.018 mV
That level of current resolution — sub-nanoamp, in the presence of high-voltage biasing — is exactly what you need when you're looking at gate oxide charge trapping.
Why does this matter?
SiC MOSFETs have a known weakness: the SiO₂/SiC interface quality is fundamentally worse than the SiO₂/Si interface in conventional silicon devices. Trapped charges at that interface shift threshold voltage, degrade transconductance, and create long-term reliability problems that don't show up in standard production testing.
The new JEDEC standards for SiC device reliability — explicitly referenced on the wall display — are starting to require quantification of these effects. The Forced Current Quasistatic CV method gives you a number. Not a qualitative "looks okay" — an actual charge density you can track over stress cycles.
This is what static characterization means at its best: → Not sweeping I-V curves and calling it done → Extracting the internal physics of the device
Station 2 → Tektronix: Dynamic Switching Power Characterization (DPT)
The DPT station was unmistakable from across the floor.
A large display running live waveforms. A transparent DUT enclosure showing the real power circuit. Multiple Tektronix oscilloscopes — 4 Series and 5 Series MSOs — connected with isolated probes. An arbitrary function generator generating the switching pulse sequence.
The waveform on the main screen showed: → Gate drive pulse (yellow) → Drain current trace → V_DS across the device → Math channel computing instantaneous power → M1 = 56.30 nJ (turn-on switching energy) → M2 = 862.1 nJ (related energy metric, likely full switching cycle or conduction loss integral)
These numbers are what SiC MOSFET datasheets promise — and what real systems often struggle to replicate.
The three key features highlighted on the wall:
→ New IsoVu™ Isolated Current Shunt Probe Standard current probes fail at high dv/dt because common-mode interference corrupts the measurement. IsoVu uses optical isolation, achieving 160 dB CMRR — 100 million to 1 common-mode rejection. The measurement arrives clean, even when V_DS is switching at hundreds of volts in nanoseconds.
→ Dynamic Rds(ON) without external clamping Conventional methods require an external clamp circuit to separate the on-state voltage from the switching transient. This introduces its own parasitics and measurement artifacts. Tektronix's approach extracts dynamic Rds(ON) directly from the waveform without that hardware intervention. The result is a measurement that reflects what the device actually does in circuit — not what it does when you add extra components to help the measurement.
→ Patented deskew algorithm Energy calculation is V × I × dt. If the voltage and current channels have different propagation delays — even 1 ns — the computed energy is wrong. The deskew algorithm aligns the channels at picosecond precision before the math is applied. This matters enormously when switching edges are in the 10–50 ns range.
The ST SiC Evaluation Board
On the same bench — a co-exhibition with STMicroelectronics.
A placard on the table identified the device: SCT060N120G3 / SCT040N120G3 SiC MOSFETs in HiP247-4 packages, on an evaluation board designed for high-speed switching reference designs.
The board configuration supported direct DPT integration: → Gate driver section at the top → DC bus capacitor bank clearly visible → SMA connectors for probe connection
This is the kind of joint demo that tells you something about where the industry is going. The device manufacturer and the measurement instrument manufacturer sharing the same table means the characterization workflow is being designed together — not retrofitted after the fact.
Why These Two Stations Are Not the Same Thing
It's easy to look at both setups and think: static first, then dynamic. A natural sequence.
But the measurement environments are fundamentally different.
In static characterization: → The device is biased slowly → Temperature is controlled or stable → Charge has time to redistribute and settle → You see the equilibrium state of the device
In dynamic switching: → Transitions happen in 10–50 ns → Temperature is rising during the pulse → Trapped charges have no time to respond → You see the transient state of the device
These are not the same device.
The same silicon carbide MOSFET behaves differently under these two conditions — and both behaviors are real. One tells you about gate oxide reliability and threshold stability. The other tells you about switching loss and dynamic resistance in actual operation.
The gap between them is not a measurement error. It is physics.
What This Means for Power Electronics Engineers
If you're developing SiC or GaN-based systems for EV inverters, industrial drives, data center power conversion, or any high-switching-frequency application — these two measurement dimensions are not optional.
Static characterization tells you if your device is what it claims to be. Dynamic characterization tells you if it performs as intended in your circuit.
Neither is sufficient without the other.
The tools to do both now exist — and the methodology to connect them is being formalized in JEDEC standards.
The question is whether your test strategy already accounts for both worlds.
All photos: Thomas · @SignalByThomas